Tech & Science SmartDV Delivers First-to-Marketplace MIPI A-PHY v1.Zero Verification IP

SmartDV Delivers First-to-Marketplace MIPI A-PHY v1.Zero Verification IP

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SAN JOSE, Calif., Sept. 22, 2020 (GLOBE NEWSWIRE) — SmartDV™ Applied sciences as soon as once more is the primary corporate to send Verification highbrow belongings (IP) to improve MIPI A-PHY v1.0, the industry-standard, long-reach serializer-deserializer (SerDes) bodily layer interface, handing over it because the MIPI Alliance introduced availability.

MIPI A-PHY v1.0’s uneven long-reach bodily layer interface bureaucracy the cornerstone of the MIPI Automobile SerDes Answers (MASS) that offer connectivity for Complex driver-assistance programs (ADAS), in-vehicle infotainment (IVI) and different surround-sensor packages. “Our swift reaction and instant availability of our MIPI A-PHY v1.Zero Verification IP firmly establishes us within the car marketplace section,” affirms Deepak Kumar Tala, managing director of SmartDV, the Confirmed and Relied on selection for Design and Verification IP. “This success is because of our proprietary, computerized compiler-based generation that guarantees our IP is compliant with usual protocol specs for brand spanking new or evolving packages.”

As with any SmartDV speedy, extremely configurable and reusable plug-and-play Verification IP, customers get to marketplace temporarily and expectantly. The MIPI A-PHY v1.Zero Verification IP can be utilized all through a coverage-driven chip design verification waft in simulation, emulation, and box programmable gate array (FPGA) prototyping. It additionally options SimXL™, Synthesizable Transactors for accelerating system-level, system-on-chip (SoC) checking out on {hardware} emulators or FPGA prototyping platforms. SimXL permits early tool building on an FPGA platform, in addition to speedy porting of simulation assessments to emulators and FPGA platforms.

A configurable bus useful type (BFM), protocol track and library of built-in protocol exams come usual with SmartDV’s Verification IP. The IP helps all main verification languages and methodologies, together with the open verification technique (OVM), common verification technique (UVM) and SystemC.

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Availability and Pricing
The SmartDV MIPI A-PHY v1.Zero Verification IP is to be had now and subsidized by way of an skilled R&D workforce that works personally with every person set up. Complex configuration and standing reporting interfaces are provided, in conjunction with a complete check suite that may be applied in ASIC, SoC or FPGA designs. 

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Pricing is to be had upon request. Rapid turnaround customization is to be had.

Electronic mail requests for datasheets or additional information must be despatched to gross [email protected].

About SmartDV
SmartDV™ Applied sciences is the Confirmed and Relied on selection for Design and Verification IP with the most efficient customer support from greater than 250 skilled ASIC and SoC design and verification engineers. SmartDV provides top of the range usual protocol Design and Verification IP for simulation, emulation, box programmable gate array (FPGA) prototyping, post-silicon validation, formal belongings verification and RISC-V CPU verification. All of its Design and Verification IP answers will also be swiftly custom designed to satisfy explicit buyer design wishes. The result’s Confirmed and Relied on Design and Verification IP utilized in masses of networking, garage, car, bus, MIPI and show chip tasks all through the worldwide electronics {industry}. SmartDV is headquartered in Bangalore, India, with U.S. headquarters in San Jose, Calif.

Hook up with SmartDV at:
Site: www.Good-DV.com
Linkedin: https://www.linkedin.com/corporate/smartdv-technologies/about/
Twitter: @SmartDV

For more info, touch:
Nanette Collins
Public Family members for SmartDV
(617) 437-1822
[email protected]

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